A variety of electronic devices incorporating first and second terminals connected by a semiconductor channel, and a gate terminal arranged with respect to the channel to control its conductivity, are known. A variety of techniques for manufacturing such electronic devices are also known. In certain of these techniques, it is desirable to manufacture the gate terminal such that it is accurately aligned in respect to the channel, so that a voltage (i.e. electric potential) can be applied to the gate terminal to control the channel conductivity to such an extent that it can effectively be switched off (i.e. such that charge flow along the channel, from one terminal to the other can be completely prevented). One known technique for producing a gate structure accurately aligned with respect to the gap between source and drain terminals of a transistor, and to the semiconductor channel bridging that gap, is to use the source and drain terminals themselves as a mask, and expose a photosensitive layer provided above the structure to radiation (such as UV radiation) from below. The exposed resist material can then be developed to remove it, forming a window in which a gate dielectric layer and then a conductive layer can be deposited to form the gate dielectric and gate terminal respectively. Such a technique is disclosed in WO 2007/110671 A2 for example. Although such techniques can provide a gate terminal accurately positioned with respect to the semiconductor channel and gap between the source and drain terminals, the problem is that gate material can be deposited over a large area, and/or there can be substantial overlap between the gate terminal and the source and drain terminals. Large overlaps are undesirable as they tend to result in large parasitic capacitances. Furthermore, it is in general undesirable to have gate terminals larger than necessary. Removal of unwanted gate material after its initial deposition represents an additional processing step, which it would be desirable to avoid if possible. WO 2007/110671 A2 discloses some attempted solutions, but these typically necessitate the positioning of a separate mask with respect to the fabricated structure whilst that structure then undergoes selective removal of gate layer material. WO 2007/110671 discloses another technique in which excessively large gate terminals may be avoided, but this involves the positioning of a shadow-mask with respect to the source-drain structure, beneath the structure, during exposure of the structure to UV radiation. The correct positioning of this shadow-mask with respect to the structure being processed represents an additional complication to the fabrication technique. Furthermore, the mask, which is separate from the structure being processed, must be held in position during the irradiation process.
Thus, WO 2007/110671 discloses a technique in which a source-drain pattern is produced, and then a reverse side exposure is used to pattern a photoresist using the source and drain as a mask. This can produce a self-aligned gate, but has the drawback that the areas not shielded by the source-drain patterns are exposed. The gate pattern may be deposited by solution processing.